HD6475348R Datasheet, PDF (15/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

10-10 Setting of Overflow Flag (OVF) ····················································································201
10-11 Square-Wave Output (Example) ····················································································206
10-12 FRC Write-Clear Contention ·························································································207
10-13 FRC Write-Increment Contention ·················································································208
10-14 Contention between OCR Write and Compare-Match ··················································209
11-1 Block Diagram of 8-Bit Timer ·······················································································214
11-2 Count Timing for External Clock Input ·········································································221
11-3 Setting of Compare-Match Flags ···················································································222
11-4 Timing of Timer Output ·································································································222
11-5 Timing of Compare-Match Clear ··················································································223
11-6 Timing of External Reset ·······························································································223
11-7 Setting of Overflow Flag (OVF) ····················································································224
11-8 Example of Pulse Output ·······························································································225
11-9 TCNT Write-Clear Contention ······················································································226
11-10 TCNT Write-Increment Contention ···············································································227
11-11 Contention between TCOR Write and Compare-Match ················································228
12-1 Block Diagram of PWM Timer ·····················································································234
12-2 PWM Timing ·················································································································239
13-1 Block Diagram of Timer Counter ··················································································242
13-2 Writing to TCNT and TCSR ··························································································247
13-3 Writing to RSTCSR ·······································································································247
13-4 Operation in Watchdog Timer Mode ·············································································249
13-5 Operation in Interval Timer Mode ·················································································249
13-6 Setting of OVF Bit ·········································································································250
13-7 Setting of WRST Bit and Internal Reset Signal ····························································251
13-8 TCNT Write-Increment Contention ···············································································252
13-9 Reset Circuit (Example) ································································································253
14-1 Block Diagram of Serial Communication Interface ······················································256
14-2 Data Format in Asynchronous Mode ·············································································271
14-3 Phase Relationship between Clock Output and Transmit Data ·····································272
14-4 Data Format in Synchronous Mode ···············································································276
14-5 Sampling Timing (Asynchronous Mode) ······································································282
15-1 Block Diagram of A/D Converter ··················································································284
15-2 Read Access to A/D Data Register (When Register Contains H'AA40) ·······················290
15-3 A/D Operation in Single Mode (When Channel 1 is Selected) ·····································293
15-4 A/D Operation in Scan Mode (When Channels 0 to 2 are Selected) ·····························295
15-5 A/D Conversion Timing ································································································296
15-6 Timing of Setting of ADST Bit ·····················································································297
16-1 Block Diagram of On-Chip RAM ·················································································299
17-1 Block Diagram of On-Chip ROM ·················································································304
17-2 (a) Socket Adapter Pin Arrangements (H8/534) ·································································306