HD6475348R Datasheet, PDF (234/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits select the internal or
external clock source for the timer counter. For the external clock source they select whether to
increment the count on the rising or falling edge of the clock input, or on both edges.
Bit 2
CKS2
0
0
0
0
1
1
1
1
Bit 1
CKS1
0
0
1
1
0
0
1
1
Bit 0
CKS0
0
1
0
1
0
1
0
1
Description
No clock source (timer stopped). (Initial value)
Internal clock source (ø/8).
Internal clock source (ø/64).
Internal clock source (ø/1024).
No clock source (timer stopped).
External clock source, counted on the rising edge.
External clock source, counted on the falling edge.
External clock source, counted on both the rising
and falling edges.
11.2.4 Timer Control/Status Register (TCSR)—H'FED1
Bit
7
6
5
4
CMFB CMFA OVF
—
Initial value
0
0
0
1
Read/Write R/(W)* R/(W)* R/(W)* —
3
OS3
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
The TCSR is an 8-bit readable and partially writable* register that indicates compare-match and
overflow status and selects the effect of compare-match events on the timer output signal (TMO).
The TCSR is initialized to H'10 at a reset and in the standby modes.
* Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits.
Bit 7—Compare-Match Flag B (CMFB): This status flag is set to 1 when the timer count
matches the time constant set in TCORB.
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