HD6475348R Datasheet, PDF (113/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

(Example)
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ADD.W R2,R0
Program flow
← DTC interrupt request
Data transfer cycle
NMI interrupt
MOV.W R0,@H'FE00
MOV.W #H'FE02,R0
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.
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After data transfer cycle, CPU
executes next instruction before
branching to exception handling
To NMI exception-handling sequence
4.9 Stack Status after Completion of Exception Handling
The status of the stack after an exception-handling sequence is described below.
Table 4-3 shows the stack after completion of the exception-handling sequence for various types
of exceptions in the minimum and maximum modes.
Table 4-3 Stack after Exception Handling Sequence
Exception Factor
Minimum Mode
Maximum Mode
Trace
SP
Interrupt
Trap
Zero divide
(DIVXU)
SR (upper byte)
SR (lower byte)
Next instruction address (upper byte)
Next instruction address (lower byte)
TP:SP
SR (upper byte)
SR (lower byte)
Don’t-care
Next instruction page (8 bits)
Next instruction address (upper byte)
Next instruction address (lower byte)
Note: The RTE instruction returns to the next instruction after the instruction being executed when
the exception occurred.
Table 4-3
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