HD6475348R Datasheet, PDF (483/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Pins A7 to A0 of the address bus and the R/W signal are initialized 1.5 ø clock periods after the
Low state of the RES pin is sampled. Pins A7 to A0 are made Low. The R/W signal is made
High.
The clock output pins P10/ø and P11/E are initialized 0.5 ø clock periods after the Low state of the
RES pin is sampled. Both pins are initialized to the output state.
P10 / ø*
RES
Internal reset signal
T1
T2
T3
T1
A7 to A0
P63 /A19 to P60/A16 and
P57 /A15 to P50/A8
R/W
AS, RD and DS (read)
H’00
High impedance
WR and DS (write)
D7 to D0 (write)
High impedance
I/O ports
High impedance
* The dotted line indicates that P10 /ø is an input port if the corresponding DDR bit is 0,
but a clock output pin if the DDR bit is 1.
Figure E-4 Reset during Memory Access (Mode 4)
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