HD6475348R Datasheet, PDF (184/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Bits 3 to 0 can be written but not read. An attempt to read these bits does not cause an error, but
all bits are read as 1, regardless of their true values.
At a reset and in the hardware standby mode, P6DDR is initialized to H'F0, making all four pins
input pins. P6DDR is not initialized in the software standby mode. In the single-chip mode, if a
P6DDR bit is set to 1 when the chip enters the software standby mode, the corresponding pin
continues to output the value in the port 6 data register.
Expanded Maximum Mode Using On-Chip ROM (Mode 4): If a 1 is set in P6DDR, the
corresponding pin is used for address output. If a 0 is set in P6DDR, the pin is used for input.
P6DDR is initialized to H'F0 at a reset and in the hardware standby mode.
Expanded Maximum Mode Not Using On-Chip ROM (Mode 3): All bits of P6DDR are fixed
at 1 and cannot be modified.
2. Port 6 Data Register (P6DR)—H'FE8B
Bit
7
6
5
4
—
—
—
—
Initial value
1
1
1
1
Read/Write
—
—
—
—
3
P63
0
R/W
2
P62
0
R/W
1
P61
0
R/W
0
P60
0
R/W
P6DR is an 8-bit register containing data for pins P63 to P60.
Bits 7 to 4 are reserved. They cannot be modified and are always read as 1.
At a reset and in the hardware standby mode, P6DR is initialized to H'F0.
When the CPU reads P6DR, for output pins it reads the value in the P6DR latch, but for input
pins, it obtains the pin status directly.
3. System Control Register 2 (SYSCR2)—H'FEFD
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
— IRQ5E IRQ4E IRQ3E IRQ2E P6PWME P9PWME P9SCI2E
1
0
0
0
0
0
0
0
—
R/W R/W R/W R/W R/W R/W R/W
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