HD6475348R Datasheet, PDF (209/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Bit 7
ICF
0
1
Description
This bit is cleared from 1 to 0 when: (Initial value)
1. The CPU reads the ICF bit after it has been set to 1, then writes a 0 in this bit.
2. The data transfer controller (DTC) serves an input capture interrupt .
This bit is set to 1 when an input capture signal causes the FRC value to be copied to the ICR.
Bit 6—Output Compare Flag B (OCFB): This status flag is set to 1 when the FRC value
matches the OCRB value.
Bit 6
OCFB
0
1
Description
This bit is cleared from 1 to 0 when: (Initial value)
1. The CPU reads the OCFB bit after it has been set to 1, then writes a 0 in this bit.
2. The data transfer controller (DTC) serves output compare interrupt B.
This bit is set to 1 when FRC = OCRB.
Bit 5—Output Compare Flag A (OCFA): This status flag is set to 1 when the FRC value
matches the OCRA value.
Bit 5
OCFA
0
1
Description
This bit is cleared from 1 to 0 when: (Initial value)
1. The CPU reads the OCFA bit after it has been set to 1, then writes a 0 in this bit.
2. The data transfer controller (DTC) serves output compare interrupt A.
This bit is set to 1 when FRC = OCRA.
Bit 4—Timer Overflow Flag (OVF): This status flag is set to 1 when the FRC overflows
(changes from H'FFFF to H'0000).
Bit 4
OVF
0
1
Description
This bit is cleared from 1 to 0 when the CPU reads (Initial value)
the OVF bit after it has been set to 1, then writes a 0 in this bit.
This bit is set to 1 when FRC changes from H'FFFF to H'0000.
Bit 3—Output Level B (OLVLB): This bit selects the logic level to be output at the FTOB pin
when the FRC and OCRB values match.
192