HD6475348R Datasheet, PDF (374/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Size
Mnemonic
Operation
B/W
Data MOV: G (EAs) → Rd
B/W
transfer
Rs → (EAd)
#IMM → (EAd)
MOV: E #IMM → Rd
(short format)
B
MOV: F @ (d: 8, FP) → Rd
B/W
Rs → @ (d: 8, FP)(short format)
MOV: I #IMM → Rd
(short format)
W
MOV: L (@aa: 8) → Rd
(short format)
B/W
MOV: S Rs → (@aa: 8) (short format)
B/W
LDM
@ SP + → Rn (register list)
W
STM
Rn (register list) → @ – SP
W
XCH
Rs ←→ Rd
W
SWAP Rd (upper byte) ←→ Rd (lower byte) B
MOVTPE Rs → (EAd) Synchronized with E clock B
MOVFPE (EAs) → Rd Synchronized with E clock B
Arith- ADD: G Rd + (EAs) → Rd
B/W
metic ADD: Q (EAd) + #IMM → (EAd)
B/W
opera-
(#IMM = ±1, ±2)
(short format)
tions ADDS Rd + (EAs) → Rd
B/W
(Rd is always word size)
ADDX Rd + (EAs) + C → Rd
B/W
DADD (Rd)10 + (Rs)10 + C → (Rd)10
B
SUB
Rd – (EAs) → Rd
B/W
SUBS Rd – (EAs) → Rd
B/W
SUBX Rd – (EAs) – C → Rd
B/W
DSUB
(Rd)10 – (Rs)10 – C → (Rd)10
B
MULXU Rd × (EAs) → Rd 8 × 8
B/W
(Unsigned)
16 × 16
DIVXU Rd ÷ (EAs) → Rd 16 ÷ 8
B/W
(Unsigned)
32 ÷ 16
CMP: G Rd – (EAs), Set CCR
B/W
(EAd) – #IMM, Set CCR
CMP: E Rd – #IMM, Set CCR (short format)
B
CMP: I Rd – #IMM, Set CCR (short format)
W
CCR Bit
N ZVC
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