HD6475348R Datasheet, PDF (80/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Specifically, the LDC.B and STC.B instructions are executed as follows.
The following applies only to the stack-pointer addressing modes. In addressing modes that do not
use the stack pointer, byte data access is performed as specified by the assembler mnemonic.
(1) STC.B EP, @–SP
When word data access is applied to EP, both EP and DP are accessed. This instruction
stores EP at address SP (old) –2, and DP at address SP (old) –1.
Old SP – 2
Old SP – 1
Old SP
EP
a
New SP
a
DP
New SP + 1
b
b
New SP + 2
Before execution
After execution
(2) LDC.B @SP+, EP
When word data access is applied to EP, both EP and DP are accessed. This instruction
loads EP from address SP (old), and DP from address SP (old) +1, updating the DP value as
well as the EP value.
EP
EP
Old SP
a
a
New SP – 2
a
Old SP + 1
b
DP
New SP – 1
DP
Old SP + 2
b
New SP
b
Before execution
After execution
(3) STC.B CCR, @–SP
When word data access is applied to CCR, only CCR is accessed. This instruction stores
identical CCR contents at both address SP (old) –2 and address SP (old) –1.
Old SP – 2
Old SP – 1
Old SP
CCR
a
New SP
a
New SP + 1
b
New SP + 2
Before execution
After execution
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