HD6475348R Datasheet, PDF (215/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

ø
FRC
N
N+1
OCR
N
Internal compare-
match signal
OCF
Figure 10-4 Setting of Output Compare Flags
Output Timing: When a compare-match occurs, the logic level selected by the output level bit
(OLVLA or OLVLB) in the TCSR is output at the output compare pin (FTOA or FTOB).
Figure 10-5 shows the timing of this operation for compare-match A.
ø
Internal compare-
match A signal
OLYLA
FTOA
Figure 10-5 Timing of Output Compare A
Fig. 10-5
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