HD6475348R Datasheet, PDF (355/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Table 20-9 (1) Control Signal Timing (R-Mask Versions)
Condition A (R-mask): VCC = 5.0 V ±10%, ø = 0.5 to 10 MHz, VSS = 0 V,
Ta = –20 to +75˚C (Regular Specifications),
Ta = –40 to +85˚C (Wide-Range Specifications)
Condition A
6 MHz
8 MHz
10 MHz
Test
Item
Symbol Min Max Min Max Min Max Unit Condition
RES setup time
RES pulse width 1*
tRESS 200 –
tRESW1 6.0 –
200 –
6.0 –
200 –
6.0 –
ns See figure
tcyc ^20-7
RES pulse width 2*
tRESW2 520 –
520 –
520 –
tcyc
RES output delay time
RES output pulse width
tRESD – 100
tRESOW 132 –
– 100
132 –
– 100 ns See figure
132 –
tcyc ^20-8
NMI setup time
NMI hold time
tNMIS
tNMIH
150 –
10 –
150 –
10 –
150 –
10 –
ns See figure
ns ^20-9
IRQ0 setup time
tIRQ0S 50 –
50 –
50 –
ns
IRQ1 setup time
tIRQ1S 50 –
50 –
50 –
ns
IRQ1 hold time
tIRQ1H 10 –
10 –
10 –
ns
A/D trigger setup time
A/D trigger hold time
tTRGS
tTRGH
50 –
10 –
50 –
10 –
50 –
10 –
ns See figure
ns ^20-22
NMI pulse width (for
recovery from software
standby mode)
tNMIW
200 –
200 –
200 –
ns
Crystal oscillator settling tOSC1
time (reset)
20 –
20 –
20 –
ms See figure
20-12
Crystal oscillator settling tOSC2
time (software standby)
10 –
10 –
10 –
ms See figure
18-1
Note: * tRESW2 applies at power-on and when the RSTOE bit in the reset control/status register
(RSTCSR) is set to 1. tRESW1 applies when RSTOE is cleared to 0.
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