HD6475348R Datasheet, PDF (89/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

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A19 –A0
AS
R/W
DS
RD
WR
D7 –D0
T1 state
Write cycle
T2 state
T3 state
Address
“High”
Write data
Figure 3-10 (b) External Access Cycle (Write Access)
3.8 CPU States
3.8.1 Overview
The CPU has five states: the program execution state, exception-handling state, bus-released
state, reset state, and power-down state. The power-down state is further divided into the sleep
mode, software standby mode, and hardware standby mode. Figure 3-11 summarizes these states,
and figure 3-12 shows a map of the state transitions.
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