HD6475348R Datasheet, PDF (244/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Contention between TCOR Write and Compare-Match: If a compare-match occurs during the
T3 state of a write cycle to TCORA or TCORB, the write takes precedence and the compare-
match signal is inhibited.
Figure 11-11 shows this type of contention.
Write cycle: CPU writes to TCORA
or TCORB
T1
T2
T3
ø
Internal address
bus
Internal write
signal
TCNT address
TCNT
N
N+1
TCORA or
N
TCORB
Compare-match
A or B signal
M
TCOR write
data
Inhibited
Figure 11-11 Contention between TCOR Write and Compare-Match
Contention between Compare-Match A and Compare-Match B: If identical time constants
are written in TCORA and TCORB, causing compare-match A and B to occur simultaneously,
any conflict between the output selections for compare-match A and B is resolved by following
the priority order in table 11-4.
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