HD6475348R Datasheet, PDF (259/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Bit 7—Overflow Flag (OVF): This bit indicates that the watchdog timer count has overflowed.
Bit 7
OVF Description
0
This bit is cleared to from 1 to 0 when the CPU reads (Initial value)
the OVF bit after it has been set to 1, then writes a 0 in this bit.
1
This bit is set to 1 when TCNT changes from H'FF to H'00.*
* OVF is not set in watchdog timer mode.
Bit 6—Timer Mode Select (WT/IT): This bit selects whether to operate in the watchdog timer
mode or interval timer mode.
Bit 6
WT/IT
0
1
Description
Interval timer mode (interval timer interrupt request)
Watchdog timer mode (reset)
(Initial value)
Bit 5—Timer Enable (TME): This bit enables or disables the timer.
Bit 5
TME
0
1
Description
TCNT is initialized to H'00 and stopped.
(Initial value)
TCNT runs. A reset or interrupt request is generated when the count overflows.
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1.
Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits select one of eight clock
sources obtained by dividing the system clock (ø).
The overflow interval listed in the table below is the time from when the watchdog timer counter
begins counting from H'00 until an overflow occurs.
244