HD6475348R Datasheet, PDF (357/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Table 20-10 Timing Conditions of On-Chip
Supporting Modules
– Preliminary for S-Mask Versions–
Condition A (R-mask):
VCC = 5.0 V ±10%, ø = 0.5 to 10 MHz, VSS = 0 V,
Ta = –20 to +75˚C(Regular Specifications),
Ta = –40 to +85˚C (Wide-Range Specifications)
Condition B (5-V S-mask): VCC = 5.0 V ±10%, ø = 2.0 to 16 MHz, VSS = 0 V,
Ta = –20 to +75˚C (Regular Specifications),
Ta = –40 to +85˚C (Wide-Range Specifications)
Condition C (3-V S-mask): VCC = 3.0 to 5.5 V, ø = 2.0 to 10 MHz, VSS = 0 V,
Ta = –20 to +75˚C (Regular Specifications)
Condition D (2.7-V S-mask): VCC = 2.7 to 5.5 V, ø = 2.0 to 8 MHz, VSS = 0 V,
Ta = –20 to +75˚C (Regular Specifications)
Item
FRT
TMR
PWM
6 MHz
Symbol Min Max
Timer output tFTOD –
100
delay time
Timer input
setup time
tFTIS
50 –
Timer clock
tFTCS 50 –
input setup time
Timer clock
pulse width
tFTCWL, 1.5 –
tFTCWH
Timer output tTMOD –
100
delay time
Timer clock
tTMCS 50 –
input setup time
Timer clock
pulse width
tTMCWL, 1.5 –
tTMCWH
Timer reset
tTMRS 50 –
input setup time
Timer output tPWOD –
100
delay time
Condition A
Condition D
8 MHz
Min Max
– 100
50 –
50 –
1.5 –
– 100
50 –
1.5 –
50 –
– 100
Condition C
10 MHz
Min Max
– 100
50 –
50 –
1.5 –
– 100
50 –
1.5 –
50 –
– 100
Condition B
16 MHz
Test
Min Max Unit Conditions
– 100 ns See figure
20-14
50 – ns
50 –
1.5 –
ns See figure
20-15
tcyc
– 100 ns See figure
20-16
50 –
ns See figure
20-17
1.5 – tcyc
50 –
ns See figure
20-18
– 100 ns See figure
20-19
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