HD6475348R Datasheet, PDF (144/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

6.5 Example
Purpose: To receive 128 bytes of serial data the serial communication interface 1.
Conditions:
• Operating mode: Minimum mode
• Received data are to be stored in consecutive addresses starting at H'FC00.
• DTC control register information for the RXI interrupt is stored at addresses H'FB80 to H'FB87.
• Accordingly, the DTC vector table contains H'FB at address H'00A2 and H'80 at address
H'00A3.
• The desired interrupt mask level in the CPU status register is 4, and the desired SCI1 interrupt
priority level is 5.
Procedure
1. The user program sets DTC control register information in addresses H'FB80 to H'FB87 as
shown in table 6-7.
Table 6-7 DTC Control Register Information Set in RAM
Address
H'FB80
H'FB82
H'FB84
H'FB86
Register
DTMR
DTSR
DTDR
DTCR
Description
Byte transfer
Source address fixed
Increment destination address
Address of SCI1 receive data register
Address H'FC00
Number of bytes to be received: 128
Value Set
H'2000
H'FEDD
H'FC00
H'0080
2. The program sets the RI (SCI1 Receive Interrupt) bit in the data transfer enable register (bit 5
of register DTEE) to 1.
3. The program sets the interrupt mask in the CPU status register to 4, and the SCI1 interrupt
priority in bits 6 to 4 of interrupt priority register IPRE to 5.
4. The program sets SCI1 to the appropriate receive mode, and sets the receive interrupt enable
(RIE) bit in the serial control register (SCR) to 1 to enable receive interrupts.
5. Thereafter, each time SCI1 receives one byte of data, it requests an RXI interrupt, which the
interrupt controller directs toward the DTC. The DTC transfers the byte from the SCI’s receive
data register (RDR) into RAM, and clears the interrupt request before ending.
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