HD6475348R Datasheet, PDF (264/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

H'FF
Watchdog timer overflow
TCNT count
H'00
Start
Internal reset signal
External reset signal
(RES)
H'00 written
to TCNT
OVF = 1
Reset
*
Start H'00 written
to TCNT
* The reset signals are output for 132 ø clock periods. The internal reset signal remains valid for 520 ø clock periods.
Figure 13-4 Operation in Watchdog Timer Mode
13.3.2 Interval Timer Mode
Interval timer operation begins when the WT/IT bit is cleared to 0 and the TME bit is set to 1.
In the interval timer mode, an interval timer interrupt request is generated each time the timer
count overflows. This function can be used to generate interrupts at regular intervals.
See figure 13-5.
H'FF
TCNT count
H'00
WT/IT = 0
*
*
*
*
TME = 1
* Interval timer interrupt request
Figure 13-5 Operation in Interval Timer Mode
Time t
*
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