HD6475348R Datasheet, PDF (376/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Mnemonic
Operation
Branch- Bcc
If condition is true then
ing
PC + disp → PC
instruc-
else next;
tions
Mnemonic
BRA
BRN
BHI
BLS
BCC
BCS
BNE
BEQ
BVC
BVS
BPL
BMI
BGE
BLT
BGT
BLE
(BT)
(BF)
(BHS)
(BLO)
Description
Always (True)
Never (False)
HIgh
Low or Same
Carry Clear (High or Same)
Carry Set (LOw)
Not Equal
EQual
oVerflow Clear
oVerflow Set
PLus
MInus
Greater or Equal
Less Than
Greater Than
Less or Equal
JMP
Effective address → PC
PJMP
Effective address → CP, PC
BSR
PC → @ – SP
PC + disp → PC
JSR
PC → @ – SP
Effective address → PC
PJSR
PC → @ – SP
CP → @ – SP
Effective address → CP, PC
RTS
@ SP + → PC
PRTS
@ SP + → CP
@ SP + → PC
RTD
@ SP + → PC
SP + #IMM → SP
PRTD @ SP + → CP
@ SP + → PC
SP + #IMM → SP
SCB
If condition is true then next;
SCB/F else Rn – 1 → Rn;
SCB/NE If Rn = –1 then next;
SCB/EQ else PC + disp → PC;
Mnemonic
SCB/F
SCB/NE
SCB/EQ
Description
Not Equal
Equal
Condition
False
Z=0
Z=1
Size CCR Bit
B/W N Z V C
— ————
Condition
True
False
C∨Z=0
C∨Z=1
C=0
C=1
Z=0
Z=1
V=0
V=1
N=0
N=1
N⊕V=0
N⊕V=1
Z ∨ (N ⊕ V) = 0
Z ∨ (N ⊕ V) = 1
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