HD6475348R Datasheet, PDF (261/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Bit 7
WRST
0
1
Description
This bit is cleared to 0 by a reset signal input from the RES pin,
(Initial state)
or when the CPU reads WRST after it has been set to 1, then writes a 0 in this bit.
This bit is set to 1 when the watchdog timer overflows in the watchdog timer mode and
an internal reset signal is generated.
Bit 6—Reset Output Enable (RSTOE): This bit selects whether the reset signal generated by a
watchdog timer overflow in the watchdog timer mode is output from the RES pin.
Bit 6
RSTOE
0
1
Description
The reset signal generated by watchdog timer overflow is not
(Initial state)
output to external devices.
The reset signal generated by watchdog timer overflow is output to external devices.
Bits 5 to 0—Reserved: These bits cannot be modified and are always read as 1.
13.2.4 Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write. The procedures for writing and reading these registers are given below.
Writing to TCNT and TCSR: These registers must be written by word access. Programs cannot
write to them by byte access. The word must contain the write data and a password.
The watchdog timer’s TCNT and TCSR registers both have the same write address. The write data
must be contained in the lower byte of the word written at this address. The upper byte must
contain H'5A (password for TCNT) or H'A5 (password for TCSR). See figure 13-2.
The result of the access depicted in figure 13-2 is to transfer the write data from the lower byte to
the TCNT or TCSR.
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