HD6475348R Datasheet, PDF (395/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

A.4.2 Tables of Instruction Execution Cycles
Tables A-7 (1) through (6) should be read as shown below:
J + K = Instruction fetch cycles.
I: Total number of bytes
written and read when
operand is in memory.
Addressing mode
Instruction
ADD.B
ADD.W
ADD:Q.B
ADD:Q.W
DADD
1
K
J
1
1
2
3
11
2
3
2
3
1 1 2 5 5 6 56 5 6 3
2 1 2 5 5 6 56 5 6
4
2 1 2 7 7 8 78 7 8
4 1 2 7 7 8 78 7 8
24
Shading in the I column means
the operand cannot be in memory.
Shading indicates addressing modes
that cannot be used with this instruction.
385