HD6475348R Datasheet, PDF (204/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Table 10-2 Register Configuration (cont)
Initial
Channel Name
Abbreviation R/W Value
Timer control register
TCR
R/W H'00
Timer control/status register
TCSR
R/(W)* H'00
Free-running counter (High)
FRC (H)
R/W H'00
Free-running counter (Low)
FRC (L)
R/W H'00
3
Output compare register A (High) OCRA (H)
R/W H'FF
Output compare register A (Low) OCRA (L)
R/W H'FF
Output compare register B (High) OCRB (H)
R/W H'FF
Output compare register B (Low) OCRB (L)
R/W H'FF
Input capture register (High)
ICR (H)
R
H'00
Input capture register (Low)
ICR (L)
R
H'00
* Software can write a 0 to clear bits 7 to 4, but cannot write a 1 in these bits.
Address
H'FEB0
H'FEB1
H'FEB2
H'FEB3
H'FEB4
H'FEB5
H'FEB6
H'FEB7
H'FEB8
H'FEB9
10.2 Register Descriptions
10.2.1 Free-Running Counter (FRC)—H'FE92, H'FEA2, H'FEB2
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Read/WriteR/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Each FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated
from a clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and
CKS0) of the timer control register (TCR).
The FRC can be cleared by compare-match A.
When the FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to 1.
Because the FRC is a 16-bit register, a temporary register (TEMP) is used when the FRC is
written or read. See section 10.3, “CPU Interface” for details.
The FRCs are initialized to H'0000 at a reset and in the standby modes.
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