HD6475348R Datasheet, PDF (16/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

17-2 (b) Socket Adapter Pin Arrangements (H8/536) ·································································307
17-3 Memory Map in PROM Mode ······················································································308
17-4 High-Speed Programming Flowchart (H8/534) ····························································309
17-5 PROM Write/Verify Timing (H8/534) ···········································································311
17-6 High-Speed Programming Flowchart (H8/536) ····························································313
17-7 PROM Write/Verify Timing (H8/536) ···········································································315
17-8 Recommended Screening Procedure ·············································································317
18-1 NMI Timing of Software Standby Mode (Application Example) ·································325
18-2 Hardware Standby Sequence ·························································································326
19-1 Execution Cycle of Instruction Synchronized with E Clock in Expanded Modes
(Maximum Synchronization Delay) ··············································································328
19-2 Execution Cycle of Instruction Synchronized with E Clock in Expanded Modes
(Minimum Synchronization Delay) ···············································································329
20-1 Example of Circuit for Driving a Darlington Transistor Pair ········································339
20-2 Example of Circuit for Driving an LED ········································································339
20-3 Output Load Circuit ·······································································································347
20-4 Basic Bus Cycle (without Wait States) in Expanded Modes ·········································351
20-5 Basic Bus Cycle (with 1 Wait State) in Expanded Modes ·············································352
20-6 Bus Cycle Synchronized with E Clock ··········································································353
20-7 Reset Input Timing ········································································································ 354
20-8 Reset Output Timing ······································································································354
20-9 Interrupt Input Timing ···································································································354
20-10 Bus Release State Timing ······························································································355
20-11 E Clock Timing ··············································································································355
20-12 Clock Oscillator Stabilization Timing ···········································································356
20-13 I/O Port Input/Output Timing ························································································357
20-14 Free-Running Timer Input/Output Timing ····································································358
20-15 External Clock Input Timing for Free-Running Timers ················································358
20-16 8-Bit Timer Output Timing ····························································································359
20-17 8-Bit Timer Clock Input Timing ····················································································359
20-18 8-Bit Timer Reset Input Timing ····················································································359
20-19 PWM Timer Output Timing ··························································································360
20-20 SCI Input Clock Timing ································································································360
20-21 SCI Input/Output Timing (Synchronous Mode) ····························································360
20-22 A/D Trigger Signal Input Timing ··················································································361
C-1 (a) Schematic Diagram of Port 1, Pin P10 ··········································································437
C-1 (b) Schematic Diagram of Port 1, Pin P11 ··········································································437
C-1 (c) Schematic Diagram of Port 1, Pin P12 ···········································································438
C-1 (d) Schematic Diagram of Port 1, Pin P13 ··········································································439
C-1 (e) Schematic Diagram of Port 1, Pin P14 ···········································································440
C-1 (f) Schematic Diagram of Port 1, Pin P15 ··········································································441