HD6475348R Datasheet, PDF (311/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Table 15-4 A/D Conversion Time (Single Mode)
Item
Synchronization delay
Input sampling time
Total A/D conversion time
Symbol
tD
tSPL
tCONV
CKS = 0
Min Typ Max
18
— 33
—
63 —
259 — 274
CKS = 1
Min Typ Max
10
— 17
—
31 —
131 — 138
Note: Values in the table are numbers of states.
15.4.4 External Triggering of A/D Conversion
A/D conversion can be started by an external trigger input.
External trigger input is enabled at the ADTRG pin when the TRGE bit in the ADCR is set to 1.
Between 1.5 and 2 ø clock cycles after the ADTRG input goes Low, the ADST bit in the ADCSR
is set to 1 and A/D conversion commences.
The timing of external triggering is shown in figure 15-6.
ø
ADTRG
1.0 to 2.0 cycles
ADST
A/D conversion
Figure 15-6 Timing of Setting of ADST Bit
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