HD6475348R Datasheet, PDF (180/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

9.6.4 Built-In MOS Pull-Up
The MOS input pull-ups of port 5 are turned on by clearing the corresponding bit in P5DDR to 0
and writing a 1 in P5DR. These pull-ups are turned off at a reset and in the hardware standby
mode. Table 9-9 indicates the status of the MOS pull-ups in various modes.
Table 9-9 Status of MOS Pull-Ups for Port 5
Mode Reset Hardware Standby Mode
1
OFF
OFF
2
3
4
7
* Including the software standby mode.
Other Operating States*
OFF
ON/OFF
OFF
ON/OFF
Notation:
OFF:
ON/OFF:
The MOS pull-up is always off.
The MOS pull-up is on when P5DDR = 0 and P5DR = 1, and off otherwise.
Note on Usage of MOS Pull-Ups
If the bit manipulation instructions listed below are executed on input/output ports 5 and 6 which
have selectable MOS pull-ups, the logic levels at input pins will be transferred to the DR latches,
causing the MOS pull-ups to be unintentionally switched on or off.
This can occur with the following bit manipulation instructions: BSET, BCLR, BNOT
(1) Specific Example (BSET Instruction): An example will be shown in which the BSET
instruction is executed for port 5 under the following conditions:
P57:
Input pin, low, MOS pull-up transistor on
P56:
Input pin, high, MOS pull-up transistor off
P55 – P50: Output pins, low
The intended purpose of this BSET instruction is to switch the output level at P50 from low
to high.
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