HD6475348R Datasheet, PDF (278/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Bit 5—Overrun Error (ORER): This bit indicates an overrun error during reception.
Bit 5
ORER
0
1
Description
This bit is cleared from 1 to 0 when:
(Initial value)
1. The CPU reads the ORER bit after it has been set to 1, then writes a 0 in this bit.
2. The chip is reset or enters a standby mode.
This bit is set to 1 if reception of the next character ends while the receive data register is
still full (RDRF = 1).
Bit 4—Framing Error (FER): This bit indicates a framing error during data reception in the
synchronous mode. It has no meaning in the asynchronous mode.
Bit 4
FER
0
1
Description
This bit is cleared to from 1 to 0 when:
(Initial value)
1. The CPU reads the FER bit after it has been set to 1, then writes a 0 in this bit.
2. The chip is reset or enters a standby mode.
This bit is set to 1 if a framing error occurs (stop bit = 0).
Bit 3—Parity Error (PER): This bit indicates a parity error during data reception in the
asynchronous mode, when a communication format with parity bits is used.
This bit has no meaning in the synchronous mode, or when a communication format without
parity bits is used.
Bit 3
PER
0
1
Description
This bit is cleared from 1 to 0 when:
(Initial value)
1. The CPU reads the PER bit after it has been set to 1, then writes a 0 in this bit.
2. The chip is reset or enters a standby mode.
This bit is set to 1 when a parity error occurs (the parity of the received data does not
match the parity selected by the bit in the SMR).
Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 1.
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