HD6475348R Datasheet, PDF (253/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Table 12-3 PWM Timer Parameters for 10 MHz System Clock
Internal Clock Frequency Resolution
ø/2
200 ns
ø/8
800 ns
ø/32
3.2 µs
ø/128
12.8 µs
ø/256
25.6 µs
ø/1024
102.4 µs
ø/2048
204.8 µs
ø/4096
409.6 µs
PWM Period
50 µs
200 µs
800 µs
3.2 ms
6.4 ms
25.6 ms
51.2 ms
102.4 ms
PWM Frequency
20 kHz
5 kHz
1.25 kHz
312.5 Hz
156.3 Hz
39.1 Hz
19.5 Hz
9.8 Hz
12.3 Operation
Figure 12-2 shows the timing of the PWM timer operation.
1. Positive Logic (OS = 0)
(1) When OE = 0—(a) in Figure 12-2: The timer count is held at H'00 and PWM output is
inhibited. (The pin is used for port 9 input/output, and its state depends on the corresponding
port 9 data register and data direction register.) Any value (such as N in figure 12-2) written
in the DTR becomes valid immediately.
(2) When OE = 1
i) The timer counter begins incrementing, and the PWM output goes High. [(b) in figure 12-2]
ii) When the count reaches the DTR value, the PWM output goes Low. [(c) in figure 12-2]
iii)If the DTR value is changed (by writing the data M in figure 12-2), the new value
becomes valid after the timer count changes from H'F9 to H'00. [(d) in figure 12-2]
2. Negative Logic (OS = 1): The operation is the same except that High and Low are reversed in
the PWM output. [(e) in figure 12-2]
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