HD6475348R Datasheet, PDF (273/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

14.2.4 Transmit Data Register (TDR)—H'FEDB, H'FEF3
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W
The TDR is an 8-bit readable/writable register that holds the next character to be transmitted.
When the TSR becomes empty, the character written in the TDR is transferred to the TSR.
Continuous data transmission is possible by writing the next byte in the TDR while the current
byte is being transmitted from the TSR.
The TDR is initialized to H'FF at a reset and in the standby modes.
14.2.5 Serial Mode Register (SMR)—H'FED8, H'FEF0
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
C/A
CHR
PE
O/E STOP
—
CKS1 CKS0
0
0
0
0
0
1
0
0
R/W R/W R/W R/W R/W
—
R/W R/W
The SMR is an 8-bit readable/writable register that controls the communication format and selects
the clock rate for the internal clock source. It is initialized to H'04 at a reset and in the standby
modes.
Bit 7—Communication Mode (C/A): This bit selects the asynchronous or synchronous
communication mode.
Bit 7
C/A
0
1
Description
Asynchronous communication.
(Initial value)
Communication is synchronized with the serial clock.
Bit 6—Character Length (CHR): This bit selects the character length in asynchronous mode. It
is ignored in synchronous mode.
Bit 6
CHR
0
1
Description
8 Bits per character.
7 Bits per character.
(Initial value)
259