HD6475348R Datasheet, PDF (236/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Bit 1
OS1
0
0
1
1
Bit 0
OS0
0
1
0
1
Description
No change when compare-match A occurs. (Initial value)
Output changes to 0 when compare-match A occurs.
Output changes to 1 when compare-match A occurs.
Output inverts (toggles) when compare-match A occurs.
11.3 Operation
11.3.1 TCNT Incrementation Timing
The timer counter increments on a pulse generated once for each period of the selected (internal or
external) clock source.
If external clock input (TMCI) is selected, the timer counter can increment on the rising edge, the
falling edge, or both edges of the external clock signal.
The external clock pulse width must be at least 1.5·ø clock periods for incrementation on a single
edge, and at least 2.5·ø clock periods for incrementation on both edges. The counter will not
increment correctly if the pulse width is shorter than these values.
ø
TMCI
Minimum TMCI Pulse Width
(Single-Edge Incrementation)
ø
TMCI
Minimum TMCI Pulse Width
(Double-Edge Incrementation)
220