HD6475348R Datasheet, PDF (237/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Figure 11-2 shows the count timing for incrementation on both edges.
ø
External clock
source
TCNT clock
pulse
TCNT
N–1
N
N+1
Figure 11-2 Count Timing for External Clock Input
11.3.2 Compare Match Timing
Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags are
set to 1 by an internal compare-match signal generated when the timer count matches the time
constant in TCORA or TCORB. The compare-match signal is generated at the last state in which
the match is true, just before the timer counter increments to a new value.
Accordingly, when the timer count matches one of the time constants, the compare-match signal is
not generated until the next period of the clock source. Figure 11-3 shows the timing of the
setting of the compare-match flags.
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