HD6475348R Datasheet, PDF (267/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

13.4 Application Notes
Contention between TCNT Write and Increment: If a timer counter clock pulse is generated
during the T3 state of a write cycle to the timer counter, the write operation takes priority and the
timer counter is not incremented. See figure 13-8.
Write cycle: CPU writes to TCNT
T1
T2
T3
ø
Internal address bus
Internal write signal
TCNT clock pulse
TCNT address
TCNT
N
M
Counter write data
Figure 13-8 TCNT Write-Increment Contention
Changing the Clock Select Bits (CKS2 to CKS0): Software should stop the watchdog timer (by
clearing the TME bit to 0) before changing the value of the clock select bits. If the clock select
bits are modified while the watchdog timer is running, the timer count may be incremented
incorrectly.
Use of Reset Output: When the reset signal is output to external devices, special circuitry is
needed for input of the external reset signal.
The reset output is an NMOS open-drain output.
Figure 13-9 shows an example of a reset circuit.
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