HD6475348R Datasheet, PDF (353/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Table 20-8 (2) Bus Timing (S-Mask Versions)
–Preliminary–
Condition B (5-V S-mask): VCC = 5.0 V ±10%, ø = 2.0 to 16 MHz, VSS = 0 V,
Ta = –20 to +75˚C (Regular Specifications),
Ta = –40 to +85˚C (Wide-Range Specifications)
Condition C (3-V S-mask): VCC = 3.0 to 5.5 V, ø = 2.0 to 10 MHz, VSS = 0 V,
Ta = –20 to +75˚C (Regular Specifications)
Condition D (2.7-V S-mask): VCC = 2.7 to 5.5 V, ø = 2.0 to 8 MHz, VSS = 0 V,
Ta = –20 to +75˚C (Regular Specifications)
Item
Symbol
Clock cycle time
tcyc
Clock pulse width Low tCL
Clock pulse width High tCH
Clock rise time
tCr
Clock fall time
tCf
Address delay time
tAD
Address hold time
tAH
Data strobe delay time 1 tDSD1
Data strobe delay time 2 tDSD2
Data strobe delay time 3 tDSD3
Write data strobe
pulse width
tDSWW
Address setup time 1 tAS1
Address setup time 2 tAS2
Read data setup time tRDS
Read data hold time
tRDH
Read data access time tACC
Write data delay time tWDD
Write data setup time tWDS
Write data hold time
tWDH
Wait setup time
tWTS
Wait hold time
tWTH
Bus request setup time tBRQS
Bus acknowledge
delay time 1
tBACD1
Condition D
8 MHz
Min Max
125 500
35 –
35 –
– 20
– 20
– 60
20 –
– 60
– 60
– 60
150 –
Condition C
10 MHz
Min Max
100 500
30 –
30 –
– 20
– 20
– 55
10 –
– 40
– 50
– 50
120 –
20 –
80 –
50 –
0–
– 190
– 75
15 –
25 –
40 –
10 –
40 –
– 60
15 –
65 –
40 –
0–
– 160
– 70
10 –
20 –
40 –
10 –
40 –
– 55
Condition B
16 MHz
Min Max
62.5 500
20 –
20 –
– 10
– 10
– 30
5–
– 30
– 30
– 30
70 –
10 –
30 –
20 –
0–
– 100
– 50
10 –
10 –
30 –
10 –
30 –
– 30
Test
Unit Conditions
ns See figure
ns ^20-4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns See figure
ns ^20-5
ns See figure
ns ^20-10
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