HD6475348R Datasheet, PDF (135/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Bit 13—DI (Destination Increment): This bit specifies whether to increment the destination
address.
Bit 13
DI
0
1
Description
Destination address is not incremented.
1) If Sz = 0: Destination address is incremented by +1 after each data transfer.
2) If Sz = 1: Destination address is incremented by +2 after each data transfer.
Bits 12 to 0—Reserved Bits: These bits are reserved.
6.2.2 Data Transfer Source Address Register (DTSR)
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read/Write — — — — — — — — — — — — — — — —
The data transfer source register is a 16-bit register that designates the data transfer source
address. For word transfer this must be an even address. In the maximum mode, this address is
implicitly located in page 0.
6.2.3 Data Transfer Destination Register (DTDR)
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read/Write — — — — — — — — — — — — — — — —
The data transfer destination register is a 16-bit register that designates the data transfer
destination address. For word transfer this must be an even address. In the maximum mode, this
address is implicitly located in page 0.
6.2.4 Data Transfer Count Register (DTCR)
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read/Write — — — — — — — — — — — — — — — —
116