HD6475348R Datasheet, PDF (446/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

MDCR—Mode Control Register
Bit
7
6
5
—
—
—
Initial value
1
1
0
Read/Write
—
—
—
H'FF12
4
3
2
1
0
—
— MDS2 MDS1 MDS0
0
0
—*
—*
—*
—
—
R
R
R
* Initialized according to the inputs at pins MD2, MD1, and MD0.
Mode Select
Value input at mode pins
SBYCR—Software Standby Control Register
H'FF13
Bit
7
6
5
4
3
2
1
0
SSBY
—
—
—
—
—
—
—
Initial value
0
1
1
1
1
1
1
1
Read/Write
R/W
—
—
—
—
—
—
—
Software Standby
0 SLEEP instruction causes transition to sleep mode.
1 SLEEP instruction causes transition to software standby mode.
RSTCSR—Reset Status/Control Register
H'FF15
WDT
Bit
7
6
5
4
3
2
1
0
WRST RSTOE —
—
—
—
—
—
Initial value
0
0
1
1
1
1
1
1
Read/Write R/(W)* R/W
—
—
—
—
—
—
Reset Output Enable
0 The reset signal is not output externally.
1 The reset signal is output externally.
Watchdog Timer Reset
0 Cleared from 1 to 0 by software, or by a Low input at the RES pin.
1 Set to 1 when TCNT overflows and a reset signal is generated.
* Software can write a 0 in bit 7 to clear the flag but cannot write a 1.
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