HD6475348R Datasheet, PDF (9/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Section 13 Watchdog Timer
13.1 Overview ····························································································································241
13.1.1 Features ···················································································································241
13.1.2 Block Diagram ········································································································242
13.1.3 Register Configuration ····························································································242
13.2 Register Descriptions ·········································································································243
13.2.1 Timer Counter TCNT—H'FEEC (Write), H'FEED (Read) ····································243
13.2.2 Timer Control/Status Register (TCSR)—H'FEEC ·················································243
13.2.3 Reset Control/Status Register (RSTCSR)—H'FF14 (Write), H'FF15 (Read) ········245
13.2.4 Notes on Register Access ························································································246
13.3 Operation ····························································································································248
13.3.1 Watchdog Timer Mode ···························································································248
13.3.2 Interval Timer Mode ·······························································································249
13.3.3 Operation in Software Standby Mode ·····································································250
13.3.4 Setting of Overflow Flag ························································································250
13.3.5 Setting of Watchdog Timer Reset (WRST) Bit ·······················································251
13.4 Application Notes ··············································································································252
Section 14 Serial Communication Interface
14.1 Overview ····························································································································255
14.1.1 Features ···················································································································255
14.1.2 Block Diagram ········································································································256
14.1.3 Input and Output Pins ·····························································································257
14.1.4 Register Configuration ····························································································257
14.2 Register Descriptions ·········································································································258
14.2.1 Receive Shift Register (RSR) ·················································································258
14.2.2 Receive Data Register (RDR)—H'FEDD, H'FEF5 ················································258
14.2.3 Transmit Shift Register (TSR) ················································································258
14.2.4 Transmit Data Register (TDR)—H'FEDB, H'FEF3 ···············································259
14.2.5 Serial Mode Register (SMR)—H'FED8, H'FEF0 ···················································259
14.2.6 Serial Control Register (SCR)—H'FEDA, H'FEF2 ················································261
14.2.7 Serial Status Register (SSR)—H'FEDC, H'FEF4 ···················································263
14.2.8 Bit Rate Register (BRR)—H'FED9, H'FEF1 ··························································265
14.3 Operation ····························································································································270
14.3.1 Overview ·················································································································270
14.3.2 Asynchronous Mode ·······························································································271
14.3.3 Synchronous Mode ·································································································275
14.4 CPU Interrupts and DTC Interrupts ···················································································279
14.5 Application Notes ··············································································································280