HD6475348R Datasheet, PDF (227/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Table 10-5 Effect of Changing Internal Clock Sources
No. Description
Timing Chart
1
Low → Low:
CKS1 and CKS0 are
rewritten while both
Old clock
source
clock sources are Low.
New clock
source
FRC clock
pulse
FRC
N
N+1
2
Low → High:
CKS1 and CKS0 are
rewritten while old
Old clock
source
clock source is Low and
new clock source is High.
New clock
source
CKS rewrite
FRC clock
pulse
FRC
N
3
High → Low:
CKS1 and CKS0 are
rewritten while old
Old clock
source
clock source is High and
new clock source is Low.
New clock
source
FRC clock
pulse
N+1
N+2
CKS rewrite
*
FRC
N
N+1
N+2
CKS rewrite
∗ The switching of clock sources is regarded as a falling edge that increments the FRC.
210