HD6475348R Datasheet, PDF (123/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

5.3 Register Descriptions
5.3.1 Interrupt Priority Registers A to F (IPRA to IPRF)
IRQ0, IRQ1 to IRQ5, and the on-chip supporting modules are each assigned three bits in one of
the six interrupt priority registers (IPRA to IPRF). These bits specify a priority level from 7
(high) to 0 (low) for interrupts from the corresponding source. The drawing below shows the
configuration of the interrupt priority registers. Table 5-3 lists their assignments to interrupt
sources.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
—
—
0
0
0
0
0
0
0
0
R
R/W R/W R/W
R
R/W R/W R/W
Note: Bits 7 and 3 are reserved. They cannot be modified and are always read as 0.
Table 5-3 Assignment of Interrupt Priority Registers
Register
IPRA
IPRB
IPRC
IPRD
IPRE
IPRF
Interrupt Request Source
Bits 6 to 4 Bits 2 to 0
IRQ0
IRQ1
IRQ2, IRQ3 IRQ4, IRQ5
FRT1
FRT2
FRT3
8-bit timer
SCI1
SCI2
A/D converter —
As table 5-3 indicates, each interrupt priority register specifies priority levels for two interrupt
sources. A user program can assign desired levels to these interrupt sources by writing “000” in
bits 6 to 4 or bits 2 to 0 to set priority level 0, for example, or “111” to set priority level 7.
A reset clears registers IPRA to IPRF to H'00, so all interrupts except NMI are initially masked.
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