HD6475348R Datasheet, PDF (226/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Contention between OCR Write and Compare-Match: If a compare-match occurs during the
T3 state of a write cycle to the lower byte of OCRA or OCRB, the write takes precedence and the
compare-match signal is inhibited.
Figure 10-14 shows this type of contention.
Write cycle: CPU writes to lower byte of OCRA or OCRB
T1
T2
T3
ø
Internal address bus
Internal write signal
OCR address
FRC
N
N+1
OCRA or OCRB
N
M
Write data
Compare-match
A or B signal
Inhibited
Figure 10-14 Contention between OCR Write and Compare-Match
Incrementation Caused by Changing of Internal Clock Source: When an internal clock
source is changed, the changeover may cause the FRC to increment. This depends on the time at
which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 10-5.
The pulse that increments the FRC is generated at the falling edge of the internal clock source. If
clock sources are changed when the old source is High and the new source is Low, as in case
No. 3 in table 10-5, the changeover generates a falling edge that triggers the FRC increment pulse.
Switching between an internal and external clock source can also cause the FRC to increment.
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