HD6475348R Datasheet, PDF (400/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Table A-7 Instruction Execution Cycles (4)
Addressing mode
Instruction
SHLR.B <EAd>
SHLR.W <EAd>
STC.B CR, <EAd>
STC.W CR, <EAd>
SUB.B <EAs >, Rd
SUB.W <EAs >, Rd
SUBS.B <EAs >, Rd
SUBS.W <EAs >, Rd
SUBX.B <EAs >, Rd
SUBX.W <EAs >, Rd
SWAP Rd
TAS <EAd>
TST.B <EAd>
TST.W <EAd>
XCH Rs , Rd
XOR.B <EAs >, Rd
XOR.W <EAs >, Rd
XORC #xx, CR
DIVXU.B Zero divide, minimum mode
DIVXU.B Zero divide, maximum mode
DIVXU.W Zero divide, minimum mode
DIVXU.W Zero divide, maximum mode
DIVXU.B Overflow
DIVXU.W Overflow
*
For register and immediate
operands
For memory operand
1
K
J
1
1
2
3
11
2
3
2
3
2 1 2 7 7 8 78 7 8
4 1 2 7 7 8 78 7 8
1 1 2 7 7 8 78 7 8
2 1 2 7 7 8 78 7 8
1 1 2 5 5 6 56 5 6 3
2 1 2 5 5 6 56 5 6
4
1 1 3 5 5 6 56 5 6 3
2 1 3 5 5 6 56 5 6
4
1 1 2 5 5 6 56 5 6 3
2 1 2 5 5 6 56 5 6
4
13
2 1 4 7 7 8 78 7 8
1 1 2 5 5 6 56 5 6
2 1 2 5 5 6 56 5 6
14
1 1 2 5 5 6 56 5 6 3
4 1 4 5 5 6 56 5 6
4
1
59
*
6
7
1
10
11
1
6
8
1
10
12
1
11
21
20 23 23 24 23 24 23 24 21
25 28 28 29 28 29 28 29 21
20 23 23 24 23 24 23 24
27
25 28 28 29 28 29 28 29
27
8 11 11 12 11 12 11 12 9
8 11 11 12 11 12 11 12
10
390