HD6475348R Datasheet, PDF (142/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Table 6-5 Number of States per Data Transfer
Increment Mode
Source Destina-
(SI)
tion (DI)
0
0
0
1
1
0
1
1
On-Chip RAM ↔Module or I/O
Register
Byte Transfer Word Transfer
31
34
33
36
33
36
35
38
Note: Numbers in the table are the number of states.
External RAM ↔ Module or I/O
Register
Byte Transfer Word Transfer
32
38
34
40
34
40
36
42
The values in table 6-5 are calculated from the formula:
N = 26 + 2 × SI + 2 × DI + MS + MD
Where MS and MD have the following meanings:
MS: Number of states for reading source data
MD: Number of states for writing destination data
The values of MS and MD depend on the data location as follows:
ΠByte or word data in on-chip RAM:
³ 2 states
 Byte data in external RAM or register field: ³ 3 states
Ž Word data in external RAM or register field: ³ 6 states
If the DTC control register information is stored in external RAM, 20 + 4 × SI + 4 × DI must be
added to the values in table 6-5.
The values given above do not include the time between the occurrence of the interrupt request
and the starting of the DTC. This time includes two states for the interrupt controller to check
priority and a variable wait until the end of the current CPU instruction. At maximum, this time
equals the sum of the values indicated for items No. 1 and 2 in table 6-6.
If the data transfer count is 0 at the end of a data transfer cycle, the number of states from the end
of the data transfer cycle until the first instruction of the user-coded interrupt-handling routine is
executed is the value given for item No. 3 in table 6-6.
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