HD6475348R Datasheet, PDF (484/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

5. Mode 7
Figure E-5 shows how the pin states change when the RES pin goes Low in mode 7.
As soon as RES goes Low, all ports are initialized to the input (high-impedance) state.
The clock output pins P10/ø and P11/E are initialized 0.5 ø clock periods after the Low state of the
RES pin is sampled. Both pins are initialized to the output state.
P10 / ø*
P10 / E*
RES
Internal reset signal
I/O ports
High impedance
* The dotted line indicates that P10 /ø and P10 /E are input ports if the corresponding DDR
bit is 0, but clock output pins if the DDR bit is 1.
Figure E-5 Reset during Memory Access (Mode 7)
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