HD6475348R Datasheet, PDF (67/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

3.4.3 Effective Address Calculation
Table 3-8 explains how the effective address is calculated in each addressing mode.
Table 3-8 Effective Address Calculation
No. Addressing Mode Effective Address Calculation Effective Address
1
Register direct
—
Operand is contents of
Rn
Rn
1010Sz rrr
2
Register indirect —
@Rn
1101Sz rrr
23
15
0
DP ^*1
Rn
Or TP or EP ^*2
3
Register indirect 8 Bits
with displacement 15
0
@(d:8,Rn)
Rn
23
15
0
DP ^*1
Result
15
0
+
Or TP or EP ^*2
1110Sz rrr
Displacement with
sign extension
@(d:16,Rn)
16 Bits
1111Sz rrr
15
0
Rn
23
15
0
DP ^*1
Result
15
0
Or TP or EP ^*2
Displacement
+
4
Register indirect 15
0
with pre-decrement
Rn
23
15
0
DP ^*1
Result
@–Rn
1011Sz rrr
1 or 2
–
Or TP or EP ^*2
Rn is decremented by –1 or –2
before instruction execution.^*3*4*5
Register indirect —
23
15
0
with post-increment
DP ^*1
Rn
@Rn+
Rn is incremented by +1 or +2
1100Sz rrr
after instruction execution.^*3*4*5 Or TP or EP ^*2
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