HD6475348R Datasheet, PDF (120/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

During the interrupt-handling routine, if the same external interrupt is requested again the request
is held, but the exception-handling sequence is not carried out immediately because the interrupt
is masked by bits I2 to I0 in the status register. On return from the interrupt-handling routine one
more instruction is executed, then the pending exception-handling sequence is carried out.
Interrupts IRQ1 to IRQ5 are served by the CPU or DTC depending on DTEA bit 0 and DTEB bits
0, 1, 4, and 5.
In the CPU interrupt exception-handling sequence for IRQ1 to IRQ5, the T bit of the CPU status
register is cleared to 0, and the interrupt mask level is set to the value in IPRA or IPRB.
Coding Examples:
To enable IRQ1 to be requested by IRQ1 input:
To assign priority level 7 to IRQ0 and level 5 to IRQ1:
To have IRQ1 start the DTC:
BSET.B #6, @H'FEFC
MOV.B #75, @H'FF00
BSET.B #0, @H'FF08
5.2.2 Internal Interrupts
Twenty-three types of internal interrupts can be requested by the on-chip supporting modules.
Each interrupt is separately vectored in the exception vector table, so it is not necessary for the
user-coded interrupt handler routine to determine which type of interrupt has occurred.
Each of the internal interrupts can be enabled or disabled by setting or clearing an enable bit in the
control register of the on-chip supporting module.
An interrupt priority level from 7 to 0 can be assigned to each on-chip supporting module by
setting interrupt priority registers C to F. Within each module, different interrupts have a fixed
priority order. For most of these interrupts, values set in data transfer enable registers C to F can
select whether to have the interrupt served by the CPU or the data transfer controller.
In the CPU interrupt-handling sequence, the T bit of the CPU status register is cleared to 0, and
the interrupt mask level in bits I2 to I0 is set to the value in the IPR. Unlike external interrupt
requests, internal interrupt requests are not held in the interrupt controller, so the bits that generate
internal interrupts must be cleared by software.
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