HD6475348R Datasheet, PDF (19/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

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Port 4 Registers ··············································································································157
Port 5 Registers ··············································································································160
Status of MOS Pull-Ups for Port 5 ················································································163
Port 6 Registers ··············································································································166
Port 6 Pin Functions in Modes 7, 2, and 1 ·····································································171
Status of MOS Pull-Ups for Port 5 ················································································172
Port 7 Registers ··············································································································173
Port 7 Pin Functions ·······································································································175
Port 8 Registers ··············································································································177
Port 9 Registers ··············································································································178
Port 9 Pin Functions ·······································································································180
Input and Output Pins of Free-Running Timer Module ················································185
Register Configuration ···································································································186
Free-Running Timer Interrupts ······················································································201
Synchronization by Writing to FRCs ·············································································202
Effect of Changing Internal Clock Sources ···································································210
Input and Output Pins of 8-Bit Timer ············································································215
8-Bit Timer Registers ·····································································································215
8-Bit Timer Interrupts ····································································································224
Priority Order of Timer Output ······················································································229
Effect of Changing Internal Clock Sources ···································································229
Output Pins of PWM Timer Module ·············································································234
PWM Timer Registers ···································································································235
PWM Timer Parameters for 10 MHz System Clock ·····················································238
Register Configuration ···································································································242
Read Addresses of TCNT and TCSR ············································································248
SCI Input/Output Pins ····································································································257
SCI Registers ·················································································································257
Examples of BRR Settings in Asynchronous Mode·······················································265
Examples of BRR Settings in Synchronous Mode ························································269
Communication Formats Used by SCI ··········································································270
SCI Clock Source Selection ···························································································270
Data Formats in Asynchronous Mode ···········································································272
Receive Errors ···············································································································275
SCI Interrupts ·················································································································280
SSR Bit States and Data Transfer When Multiple Receive Errors Occur ·····················281
A/D Input Pins ···············································································································285
A/D Registers ·················································································································285
Assignment of Data Registers to Analog Input Channels ·············································286
A/D Conversion Time (Single Mode) ···········································································297
RAM Control Register ···································································································300