HD6475348R Datasheet, PDF (310/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

15.4.3 Input Sampling Time and A/D Conversion Time
The A/D converter includes a built-in sample-and-hold circuit. Sampling of the input starts at a
time tD after the ADST bit is set to 1. The sampling process lasts for a time tSPL. The actual A/D
conversion begins after sampling is completed. Figure 15-5 shows the timing of these steps, and
table 15-4 lists the total conversion times (tCONV) for the single mode.
The total conversion time includes tD and tSPL. The purpose of tD is to synchronize the ADCSR
write time with the A/D conversion process, so the length of tD is variable. The total conversion
time therefore varies within the minimum to maximum ranges indicated in table 15-4.
In the scan mode, the ranges given in table 15-4 apply to the first conversion. The length of the
second and subsequent conversion processes is fixed at 256 states (when CKS = 0) or 128 states
(when CKS = 1).
(1)
ø
Internal address
bus
(2)
Write signal
Input sampling
timing
ADF
tD
tSPL
tCONV
(1)
(2)
tD
t SPL
t CONV
: ADCSR write cycle
: ADCSR address
: Synchronization delay
: Input sampling time
: Total A/D conversion time
Figure 15-5 A/D Conversion Timing
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