HD6475348R Datasheet, PDF (356/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Table 20-9 (2) Control Signal Timing (S-Mask Versions)
–Preliminary–
Condition B (5-V S-mask): VCC = 5.0 V ±10%, ø = 2.0 to 16 MHz, VSS = 0 V,
Ta = –20 to +75˚C (Regular Specifications),
Ta = –40 to +85˚C (Wide-Range Specifications)
Condition C (3-V S-mask): VCC = 3.0 to 5.5 V, ø = 2.0 to 10 MHz, VSS = 0 V,
Ta = –20 to +75˚C (Regular Specifications)
Condition D (2.7-V S-mask): VCC = 2.7 to 5.5 V, ø = 2.0 to 8 MHz, VSS = 0 V,
Ta = –20 to +75˚C (Regular Specifications)
Condition D Condition C Condition B
Item
8 MHz
Symbol Min Max
10 MHz
Min Max
16 MHz
Min Max Unit
Test
Conditions
RES setup time
RES pulse width 1*
tRESS
tRESW1
200 –
6.0 –
200 –
6.0 –
200 – ns
See figure
6.0 –
tcyc
20-7
RES pulse width 2* tRESW2 520 –
520 –
520 –
tcyc
RES output delay time tRESD – 100
RES output pulse width tRESOW 132 –
– 100
132 –
– 100 ns
132 –
tcyc
See figure
20-8
NMI setup time
NMI hold time
tNMIS
tNMIH
200 –
10 –
200 –
10 –
150 – ns
10 – ns
See figure
20-9
IRQ0 setup time
tIRQ0S
50 –
50 –
50 – ns
IRQ1 setup time
tIRQ1S
50 –
50 –
50 – ns
IRQ1 hold time
tIRQ1H 10 –
10 –
10 – ns
A/D trigger setup time tTRGS
A/D trigger hold time tTRGH
50 –
10 –
50 –
10 –
50 – ns
10 – ns
See figure
20-22
NMI pulse width
(for recovery from
software standby
mode)
tNMIW
200 –
200 –
200 – ns
Crystal oscillator
settling time (reset)
tOSC1
20 –
20 –
20 –
ms
See figure
20-12
Crystal oscillator
settling time
(software standby)
tOSC2
10 –
10 –
10 –
ms
See figure
18-1
Note: * tRESW2 applies at power-on and when the RSTOE bit in the reset contol/status register
(RSTCSR) is set to 1. tRESW1 applies when RSTOE is cleared to 0.
345