HD6475348R Datasheet, PDF (136/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

The data transfer count register is a 16-bit register that counts the number of bytes or words of
data remaining to be transferred. The initial count can be set from 1 to 65,536. A register value
of 0 designates an initial count of 65,536.
The data transfer count register is decremented automatically after each byte or word is transferred.
When its value reaches 0, indicating that the designated number of bytes or words have been
transferred, a CPU interrupt is generated with the vector of the interrupt that requested the data transfer.
6.2.5 Data Transfer Enable Registers A to F (DTEA to DTEF)
These six registers designate whether an interrupt starts the DTC. The bits in these registers are
assigned to interrupts as indicated in table 6-3. No bits are assigned to the NMI, FOVI, OVI, and
ERI interrupts, which cannot request data transfers.
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
Table 6-3 Assignment of Data Transfer Enable Registers
Interrupt
Interrupt
Source or
Source or
Register Module Bits 7 to 4
Module Bits 3 to 0
7
6
5
4
3
2
DTEA IRQ0
— — — IRQ0 IRQ1
——
1
0
— IRQ1
DTEB IRQ2, IRQ3
— — IRQ3 IRQ2 IRQ4, IRQ5 — — IRQ5 IRQ4
DTEC 16-Bit FRT1 — OCIB1 OCIA1 ICI1 16-Bit FRT2 — OCIB2 OCIA2 ICI2
DTED 16-Bit FRT3 — OCIB3 OCIA3 ICI3 8-Bit Timer — — CMIB CMIA
DTEE SCI1
— TXI1 RXI1 — SCI2
— TXI2 RXI2 —
DTEF A/D converter — — — ADI
————
Note: Bits marked “—” should always be cleared to 0.
If the bit for a certain interrupt is set to 1, that interrupt is regarded as a request for DTC service.
If the bit is cleared to 0, the interrupt is regarded as a CPU interrupt request.
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