HD6475348R Datasheet, PDF (13/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Figures
1-1 Block Diagram ···················································································································5
1-2 Pin Arrangement (CP-84, Top View) ················································································6
1-3 Pin Arrangement (CG-84, Top View) ················································································7
1-4 Pin Arrangement (FP-80A, TFP-80C, Top View) ·····························································8
2-1 H8/534 Memory Map in Each Operating Mode ······························································28
2-2 H8/536 Memory Map in Each Operating Mode ······························································29
3-1 CPU Operating Modes ·····································································································32
3-2 Registers in the CPU ········································································································33
3-3 Stack Pointer ····················································································································34
3-4 Combinations of Page Registers with Other Registers ····················································38
3-5 Short Absolute Addressing Mode and Base Register ······················································39
3-6 On-Chip Memory Access Timing ····················································································64
3-7 Pin States during Access to On-Chip Memory ································································65
3-8 Register Field Access Timing ··························································································66
3-9 Pin States during Register Field Access ··········································································67
3-10 (a) External Access Cycle (Read Access) ·············································································68
3-10 (b) External Access Cycle (Write Access) ············································································69
3-11 Operating States ···············································································································70
3-12 State Transitions ··············································································································71
3-13 Bus-Right Release Cycle (During On-chip Memory Access Cycle) ·······························73
3-14 Bus-Right Release Cycle (During External Access Cycle) ·············································74
3-15 Bus-Right Release Cycle (During Internal CPU Operation) ···········································75
4-1 Types of Factors Causing Exception Handling ·······························································81
4-2 Reset Vector ·····················································································································84
4-3 Reset Sequence (Minimum Mode, On-Chip Memory) ···················································85
4-4 Reset Sequence (Maximum Mode, External Memory) ···················································86
4-5 Interrupt Sources (and Number of Interrupt Types) ························································90
5-1 Interrupt Controller Block Diagram ················································································98
5-2 Interrupt Handling Flowchart ························································································107
5-3 (a) Stack before and after Interrupt Exception-Handling (Minimum Mode) ······················108
5-3 (b) Stack before and after Interrupt Exception-Handling (Maximum Mode) ·····················109
5-4 Interrupt Sequence (Minimum Mode, On-Chip Memory) ············································110
5-5 Interrupt Sequence (Maximum Mode, External Memory) ············································111
6-1 Block Diagram of Data Transfer Controller ··································································114
6-2 Flowchart of Data Transfer Cycle ··················································································119
6-3 DTC Vector Table ··········································································································120
6-4 DTC Vector Table Entry ································································································121
6-5 Order of Register Information ·······················································································122
6-6 Use of DTC to Receive Data via Serial Communication Interface 1 ····························126
7-1 Block Diagram of Wait-State Controller ·······································································128