HD6475348R Datasheet, PDF (103/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

4.2 Reset
4.2.1 Overview
A reset has the highest exception-handling priority.
When the RES pin goes Low, all current processing is halted and the H8/534 or H8/536 chip
enters the reset state.
A reset initializes the internal status of the CPU and the registers of the on-chip supporting
modules and I/O ports. It does not initialize the on-chip RAM.
When the RES pin returns from Low to High, the chip comes out of the reset state and begins
executing the hardware reset sequence.
4.2.2 Reset Sequence
The Reset signal is detected when the RES pin goes Low.
To ensure that the H8/534 or H8/536 is reset, the RES pin should be held Low for at least 20 ms at
power-up. To reset the H8/534 or H8/536 during operation, the RES pin should be held Low for
at least 6 system clock cycles. See table D-1, “Status of Ports” in appendix D for the status of
other pins in the reset state.
When the RES pin returns to the High state after being held Low for the necessary time, the
hardware reset exception-handling sequence begins, during which:
1. In the status register (SR), the T bit is cleared to disable the trace mode, and the interrupt mask
level (bits I2 to I0) is set to 7. A reset disables all interrupts, including NMI.
2. The CPU loads the reset start address from the vector table into the program counter and begins
executing the program at that address.
The contents of the vector table differs between minimum mode and maximum mode as indicated
in figure 4-2. This affects step 3 as follows:
Minimum Mode: One word is copied from addresses H'0000 and H'0001 in the vector table to
the program counter. Program execution then begins from the address in the program counter
(PC).
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