HD6475348R Datasheet, PDF (51/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Section 3 CPU
3.1 Overview
The H8/534 and H8/536 have the H8/500 Family CPU: a high-speed central processing unit
designed for realtime control of a wide range of medium-scale office and industrial equipment. Its
Hitachi-original architecture features eight 16-bit general registers, internal 16-bit data paths, and
an optimized instruction set.
Section 3 summarizes the CPU architecture and instruction set.
3.1.1 Features
The main features of the H8/500 CPU are listed below.
• General-register machine
— Eight 16-bit general registers
— Seven control registers (two 16-bit registers, five 8-bit registers)
• High speed: maximum 16 MHz (S-mask versions)
At 16 MHz a register-register add operation takes only 125 ns.
• Address space managed in 64-kbyte pages, expandable to 1 Mbyte*
Page registers make four pages available simultaneously: a code page, stack page, data page,
and extended page.
• Two CPU operating modes:
— Minimum mode: Maximum 64-kbyte address space
— Maximum mode: Maximum 1 Mbyte address space*
• Highly orthogonal instruction set
Addressing modes and data sizes can be specified independently within each instruction.
• 1.5 Addressing modes
Register-register and register-memory operations are supported.
• Optimized for efficient programming in C language
In addition to the general registers and orthogonal instruction set, the CPU has special short
formats for frequently-used instructions and addressing modes.
* The CPU architecture supports up to 16 Mbytes of external memory, but the H8/534 and
H8/536 have only enough address pins to address 1 Mbyte.
31