HD6475348R Datasheet, PDF (139/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

6.3.2 DTC Vector Table
The DTC vector table is located immediately following the exception vector table at the beginning
of page 0 in memory. For each interrupt that can request DTC service, the DTC vector table
provides a pointer to an address in memory where the table of DTC control register information
for that interrupt is stored. The register information tables can be placed in any available locations
in page 0.
Vector table
RAM
Exception
vector table
Register
information table
TA0
0
DTMR0
DTSR0
DTDR0
DTCR0
TA0
TA1
DTC vector
table
Register
TA1
information table
1
DTMR1
DTSR1
DTDR1
DTCR1
Note: TA0, TA1, ...: Addresses of DTC register information tables in memory.
Note: TA0, TA1,... : Addresses of DTC register information tables in memory.
Normally the register information tables are placed on RAM. If software does not
need to modify the register information (addresses are fixed and transfer count is 1),
it can be placed on ROM.
Figure 6-3 DTC Vector Table
In minimum mode, each entry in the DTC vector table consists of two bytes, pointing to an
address in page 0. In maximum mode, for compatibility reasons, each DTC vector table entry
consists of four bytes but the first two bytes are ignored; the last two bytes point to an address
which is implicitly assumed to be in page 0, regardless of the current page specifications.
Figure 6-4 shows one DTC vector table entry in minimum and maximum mode.
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