HD6475348R Datasheet, PDF (257/487 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

13.1.2 Block Diagram
Figure 13-1 is a block diagram of the watchdog timer.
Interrupt signal
Interval timer mode
Interrupt
control
Overflow
TCNT
TCSR
Reset
(internal, external)
RSTCSR
Reset control
TCNT : Timer Counter
TCSR : Timer Control/Status Register
RSTCSR : Reset Control/Status Register
Clock _Clock
select
Read/ ^{Internal data bus}
write
control
Internal clock sources
ø/2
ø/32
ø/64
ø/128
ø/256
ø/512
ø/2048
ø/4096
Figure 13-1 Block Diagram of Timer Counter
13.1.3 Register Configuration
Table 13-1 lists information on the watchdog timer registers.
Table 13-1 Register Configuration
Initial
Addresses
Name
Abbreviation R/W Value Write
Read
Timer control/status register TCSR
R/(W)* H'18
H'FEEC H'FEEC
Timer counter
TCNT
R/W H'00
H'FEEC H'FEED
Reset control/status register RSTCSR
R/(W)* H'3F
H'FF14 H'FF15
* Software can write a 0 to clear the status flag bits, but cannot write 1.
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